1. Field of the Invention
The present invention relates to a bit synchronization method and a bit synchronization device for extracting an output data signal and an output clock signal from an input data signal with a multi-phase clock signal, and more particularly to a bit synchronization method and a bit synchronization device for holding a phase of a change point of an input date signal with a multi-phase clock signal and selecting a clock signal having a phase free from the change point for the execution of the data identification.
2. Description of the Related Art
Conventionally, in a data transmission/reception used in a wide band ISDN (B-ISDN) or the like, it is required to receive a digital transmission signal in which phase variation is generated without the generation of an error in data identification. In such a digital transmission, synchronization is established with the same clock signal from a clock signal supply source to transmit data. As such a bit synchronization device, there is known an example in which a digital phase locked loop (DPLL) is used for taking bit synchronization with a multi-phase clock signal.
As such a bit synchronization device, Japanese Patent Application Laid-Open (JP-A) No. 62-43919 describes xe2x80x9ca PLL circuit based on a multi-phase clockxe2x80x9d. In this conventional example, a phase comparison value between the received data and an extracted clock signal extracted with a closed loop is counted up and down thereby selecting an extracted clock signal from multi-phase clock signals which have the same frequency at this count value and which have phases shifted every N number. Thus, the extracted clock signals are obtained which are synchronized in phase with the received data by repeating the series of operations.
It sometimes happens that such a bit synchronization circuit is put in an abnormal oscillating state in a positive feedback thereof without the convergence of the phase synchronization operation by delay of the closed loop. Furthermore, when received data having a jitter (a short cycle phase shift) generated therein is input, the synchronization between the received data and the extracted clock signal is broken.
In other words, in an example in which such a PLL circuit is used, a jitter which is overlapped on the input data transmission is transmitted to the extracted clock signal. As a consequence, a jitter is generated in the extracted clock signal due to an influence of the input data, and furthermore the jitter is amplified and an abnormally oscillating state is generated in some cases. Therefore, the jitter is generated in the extracted clock signal with the result that a phase margin is reduced by the jitter portion as compared with an identification phase margin with respect to the actual input data. As a consequence, in identification data in a high-speed operation and in an environment in which the amount of noises is much the data identification becomes difficult.
As a proposal for solving the problems caused by such a closed loop, the Japanese Patent Application Laid-Open (JP-A) No. 9-233061 describes a xe2x80x9cbit synchronization circuitxe2x80x9d. In this conventional example, phase synchronization is taken on the basis of the result of the phase comparison between received data and the multi-phase clock signal, and a delay in the phase synchronization operation is prevented by an open loop configuration. That is, an abnormally oscillating state is prevented from being generated by a high-speed convergence with the open loop configuration. Also, since the extracted clock signal and the received data can be output from the multi-phase clock signal with an average value of the phases of the result of the phase comparisons from the past up to the present, the extracted clock in which the phase synchronization is established can be obtained, even when received data with a jitter is input. consequently, the received data with no timing error can be output.
However, in xe2x80x9cthe bit synchronization circuitxe2x80x9d described in the Japanese Patent Application Laid-Open (JP-A) No. 9-233061, a phase comparison between the received data and the multi-phase clock signal is performed so that a jitter is generated in the phase comparison output. In other words, there remains a room for improvement to be made on such a bit synchronization circuit in order to obtain more stable and more accurate output data signal and output clock signal from the input data signal.
An object of the present invention is to provide a bit synchronization method and a bit synchronization device which are capable of performing data identification free from an error irrespective of a jitter amplitude and a jitter frequency of an input data signal and a duty depreciation amount, and which are capable of obtaining stable and accurate output data signal and output clock signal from the input signal in which there is no frequency dependency in the jitter transmission characteristic to the output clock signal extracted from the input data signal and an abnormally oscillating state as will occur in the jitter amplification is not generated.
According to one aspect of the present invention, a bit synchronization method in which an output signal and an output clock signal are extracted from an input data signal based on a multi-phase clock signal comprises the steps of: outputting a logical value indicating a phase of a multi-phase clock signal corresponding to a phase of a change point detected from an input data signal; and holding the logical value and outputting a held phase signal in which the logical value is interpolated between logical values of a former and a latter. The method further comprises the steps of: outputting an identification phase signal in which a phase free from an identification error is determined from the multi-phase clock signal based on the held phase signal; outputting an output clock signal selected from the multi-phase clock signal corresponding to a phase indicated by the identification phase signal; outputting an output data signal in which the input data signal is identified based on the output clock signal; and releasing the held logical value and outputting a signal for determining an identification phase at a time of outputting the identification phase signal after a lapse of a definite period of time in a case where a total number of phases in which the change points are detected exceeds a set value.
According to another aspect on the present invention, a bit synchronization device which extracts an output signal and an output clock signal from an input data signal based on a multi-phase clock signal comprises a processing circuit which holds a phase corresponding to a change point of an input data signal with a multi-phase clock signal, and while the input data has a phase without change point, carrying out a data identification free from an error by selecting a clock signal corresponds to the phase without change point.
Such a bit synchronization method and such a synchronization device according to the present invention hold the phase of the change point of the input data signal with the multi-phase clock signal, and identify the input data by selecting the clock signal having a phase free from the change point at the time of extracting the output data signal and the output clock signal from the input data signal with the multi-phase clock signal.
As a result, the data identification free from an error can be performed irrespective of the jitter amplitude, the jitter frequency, and the duty depreciation amount of the input data signal. Furthermore, the jitter transmission characteristic to the output signal extracted from the input data signal does not depend on the frequency, and an abnormally oscillating state as can be observed in the amplification of the jitter is not generated. Therefore, a stable and accurate output data and output clock signal can be obtained from the input data signal.